ERSA’2007
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

ERSA’07 Final Programme

ERSA’07 Distinguished Papers

1. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs
   Jens Hagemeyer, Boris Kettelhoit, Markus Koester, Mario Porrmann
   University of Paderborn, Germany

Abstract

Dynamic reconfiguration is a promising approach to enhance the resource efficiency of FPGAs beyond the current possibilities. One of the main prerequisites for its implementation is a communication infrastructure that enables data transfer between the hardware modules that are placed on the FPGA at run-time. In this paper we present a new communication macro for Xilinx FPGAs that considers the special requirements of these systems. While most solutions that have been presented so far enable basic communication between a low number of hardware modules at fixed positions, our approach implements an infrastructure that enables free placement of hardware modules at run-time. Methodologies like 2D-placement of modules, which have been analyzed mainly in theory so far, can now be implemented with currently available FPGAs. A tool-flow is presented, that automatically generates the required homogeneous communication infrastructure for any FPGA of the Xlinx Virtex-2 to Virtex-5 family. Performance and area requirements are analyzed based on two typical example implementations of a Wishbone bus.

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2. Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors
   Pranav Vaidya, Jaehwan John Lee
   Purdue University, USA

Abstract

In the future high performance computing systems may consist of multiple processors and reconfigurable logic co-processors. Industry trends indicate that such coprocessors will be integrated on existing motherboards without any glue logic. Due to these trends, it is likely that such hybrid computing machines will be a breakthrough for various high performance applications. Thus, it has become essential to investigate the system architectures of such machines. This paper describes a full-system simulation approach to model and evaluate hybrid computing systems made up of multiple processors and coarse-grained reconfigurable logic coprocessors. We develop a full-system simulator for such hybrid machines by extending an existing full-system simulator to have device models for multicontext coarse-grained reconfigurable logic co-processors. The proposed full-system simulator is able to execute an unmodified multiprocessor operating system and a multi-band filtering application. Using this full-system simulation approach, we have investigated the tradeoffs among various system architectures.