An Integrated Platform For Heterogeneous Reconfigurable Computing
Dr. Bernhard Pottier, Univ. of Bretagne Occidentale, France
Tuesday: 11:30 - 12:15am
Room: Gold Room
Abstract
The use of reconfigurable technologies inside System on Chips (SoC) is just beginning. A number of problems are to be solved, such as obtaining fast and stable development methods, integration of different reconfigurable grains, balance between computing power, data availability and application needs. Furthermore, user friendly programming is totally lacking.
In this talk, we will describe hardware aspects of the MORPHEUS platform: architecture, communication support, 3 different reconfigurable engines (RE) and RE wrappers embedding local memories. An open software architecture brings together a general purpose compiler, an RTOS, a main memory to local memory transport mechanism and a normalized structure for synthesis tools targeting RE based kernels. The objective is to enable the concept of specific compute intensive processors working on main memory.
The tools common entry point is a CDFG data structure supporting high level language constructs, hierarchies, and concurrency. This CDFG can be addressed by compilers using an API available in different syntax.
A second layer of the tools maps the CDFG to hardware resources that are described using a common architecture model. The mapping is then copied into technology tools for the different RE that produce configuration files merged with the general purpose program code.
MORPHEUS is expected to produce the first heterogeneous reconfigurable HW/SW platform promoting software centric development methods for reconfigurable SoC. The 'spatial' tool structure preserve language and target architecture independence, it also embeds packet communication mechanism close to message passing allowing to tune synthesis of application circuits consistently with the effective condition of use.
Bio
Dr Bernard Pottier has been an early actor in reconfigurable computing with the design of a multiprocessor embedding an FPGA ring, and high level tools to program this machine (1989). Then, portability of designs and synthesis were the focus of the Madeo CAD project, completely developped in Smalltalk-80, to obtain an high degree of genericity of algorithms in relation with FPGA architecture models (2002). Madeo is used to produce quick CAD implementations, including nanotechnologies, and compact logic solutions on alternative arithmetics. Today activities are back at the system level, with coarse grain modeling of applications in terms of CDFG, and modeling of communications between memories. This research is fixed in two european projects, weakly programmable processor arrays, and the Integrated Project MORPHEUS that explores heterogeneous reconfigurable systems and their related programming methods.
