Scientific Computing using Reconfigurable Hardware
Prof. Viktor K. Prasanna, University of Southern California, USA
Wednesday: 11:00 - 11:45am
Room: Gold Room
Abstract
Reconfigurable hardware such as FPGAs(Field Programmable Gate Arrays) offer the potential for superior performance. Until recently, they have been primarily used in fixed point computations. However, several state of the art high end platforms incorporate FPGAs for application acceleration. We develop algorithmic optimizations for such systems and demonstrate the suitability of FPGAs for floating point intensive computations. We consider several kernels in linear algebra and demonstrate efficient algorithms and implementations for these on FPGAs augmented sytems. We discuss the design of a BLAS libarary for such systems and develop a highly optimized reduction circuit for such architectures. The performance of FPGAs is also compared against those of state-of-the-art embedded processors, general purpose processors, and DSPs for floating point intensive applications.
Bio
Viktor K. Prasanna (V. K. Prasanna Kumar) is Professor of Electrical Engineering and Professor of Computer Science at the University of Southern California (USC). He is an associate member of the Center for Applied Mathematical Sciences (CAMS) and a member of USC-Chevron Center of Excellence for Research and Academic Training on Interactive Smart Oilfield Technologies (CiSoft) at USC. His research interests include High Performance Computing, Parallel and Distributed Systems, Reconfigurable Computing, Network Computing and Embedded Systems. He received his BS in Electronics Engineering from the Bangalore University, MS from the School of Automation, Indian Institute of Science and Ph.D in Computer Science from the Pennsylvania State University.
Prasanna has published extensively and consulted for industries in the above areas. He is the Steering Committee Co-Chair of the International Parallel & Distributed Processing Symposium (IPDPS) [merged IEEE International Parallel Processing Symposium (IPPS) and Symposium on Parallel and Distributed Processing (SPDP)]. He is the Steering Committee Chair of the International Conference on High Performance Computing (HiPC). In the past, he has served on the editorial boards of the IEEE Transactions on VLSI, IEEE Transactions on Parallel Distributed Computing and the Proceedings of the IEEE. He serves on the editorial boards of the Journal of Parallel and Distributed Computing and the Journal of Pervasive and Mobile Computing. During 2003-'06, he was the Editor-in-Chief of the IEEE Transactions on Computers. He was the founding chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is a Fellow of the IEEE. He is a receipient of the 2005 Okawa Foundation Grant.
