ERSA’2007
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

Conference Programme

Technical Sessions

Session A:   Reconfigurable Systems on Chip
Chair:   Dr Markus Köster
Univ. of Paderborn, Germany

1. Energy-Efficient Dynamic Task Scheduling Algorithm for Reconfigurable System-on-Chip Architectures
   Swathi T. Gurumani, B. Earl Wells
   The University of Alabama in Huntsville, USA
2. Power Efficient Domain-Specific Reconfigurable Architectures for System-on-Chip Applications
   Arjun K Pai and Khaled Benkrid
   Queen's University Belfast, United Kingdom
3. Memory Hierarchy for MCSoPC Multithreaded Systems
   Erik Anderson, Wesley Peck, Jim Stevens, Jason Agron, Fabrice Baijot, Seth Warn, David Andrews
   University of Kansas, USA
4. Design Space Exploration of Multiprocessor Systems with MultiContext Reconfigurable Co-Processors
   Pranav Vaidya, Jaehwan John Lee
   Purdue University, USA
5. Energy-Aware System Synthesis for Reconfigurable Chip Multiprocessors
   Xiaofang Wang, Sotirios G Ziavras, Jie Hu1
   New Jersey Institute of Technology, USA

Session B:   Task Scheduling and Dynamic Reconfiguration
Chair:   Prof. David Andrews
Univ. of Kansas, USA

1. HW implementation of a task manager for reconfigurable systems
   Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Jose Luis Garcia, Daniel Mozos
   Universidad Complutense de Madrid, Spain
2. Task Partitioning for the Scheduling on Reconfigurable Systems driven by Specification Self-Similarity
   Matteo Giani, Massimo Redaelli, Marco D. Santambrogio, Donatella Sciuto
   Politecnico di Milano, Italy
3. Configuration and Data Scheduling for Executing Dynamic Applications onto Multi-Context Reconfigurable Architectures
   F. Rivera, M. Sanchez-Elez, N. Bagherzadeh
   Depto. Arquitectura de Computadores y Automatica, Spain
4. A Compiler to Generate Hardware from Java Byte Codes for High Performance, Low Energy Embedded Systems
   Darrin Hanna, Michael DuChene, Lawrence Kennedy, and Brian Carpenter
   Oakland University, USA
5. Design of Homogeneous Communication Infrastructures for Partially Reconfigurable FPGAs
   Jens Hagemeyer, Boris Kettelhoit, Markus Köster, Mario Porrmann
   University of Paderborn, Germany
6. Selecting Heterogeneous Computation Blocks for Reconfigurable JPEG Codec Computing
   Wei-Ting Wang, Wai-Hong Tam, Yi-Chi Chen, Kuen-Cheng Chiang, Chung-Ping Chung
   National Chiao Tung University, Taiwan, ROC

Session C:   Applications
Chair: Dr Jaehwan John Lee
Purdue Univ., USA

1. High-Precision BLAS on FPGA-enhanced Computers
   Chuan He*, Guan Qin*, and Richard E. Ewing*, Wei Zhao**
   *Texas A&M University, USA
   **Rensselaer Polytechnic Institute, USA
2. A Scalable and Reconfigurable Shared-Memory Graphics Cluster Architecture
   Ross Brennan and Michael Manzke and Keith O'Conor and John Dingliana and Carol O'Sullivan
   Trinity College Dublin, Ireland
3. High Efficiency Protection Solution for Off-Chip Memory in Embedded Systems
   Romain Vaslin *, Guy Gogniat *, Jean-Philippe Diguet * Russell Tessier**, Wayne Burleson**
   *LESTER - Centre de recherche, France
   **University of Massachusetts, USA
4. Efficient FPGA based Implementation of Time and Frequency Synchronization for MIMO-OFDM
   Jeoong Sung Park*, Hong Jip Jung**
   *Silicon Image Inc. Sunnyvale, CA, USA
   **Samsung Electronics, Seoul, Korea
5. Simulation Framework for Performance Prediction in the Engineering of Reconfigurable Systems and Applications
   Eric Grobelny, Casey Reardon, Adam Jacobs, and Alan D. George
   University of Florida, USA
6. FPGA Implementation of Analytic Design Method for a Cycle-Optimal 2-D DCT/IDCT
   E. Amoo and Clay S Gloster, Jr.
   Howard University, Washington, DC, USA
7. Prototyping of a Two-Phase Micropipeline on FPGAs
   Abdel Ejnioui
   University of South Florida, USA

Session D:   Reconfigurable Hardware
Chair:   Prof. Paul Chow
Univ. of Toronto, Canada

1. Feasibility of Hardware Acceleration of a Neocortex Model
   Sébastien Lafontant*, Tarek M. Taha**
   *IBM, USA
   ** Clemson University, USA
2. Latency Optimization for a Reconfigurable, Self-Timed, and Bit-Serial Architecture
   Achim Rettberg, Florian Dittmann, Raphael Weber
   University Paderorn, Germany
3. An FPGA Implementation of Reciprocal Sums for SPME
   Sam Lee, Paul Chow
   University of Toronto, Canada
4. Optimization of Shared High-Performance Reconfigurable Computing Resources
   Melissa C. Smith *, Gregory D. Peterson **,
   * Clemson University, USA
   ** University of Tennessee, USA
5. 272 gate count optically differential reconfigurable gate array VLSI
   Minoru Watanabe, Takenori Shiki, and Fuminori Kobayashi
   Kyushu Institute of Technology, Japan
6. Computation Patterns Identification for Instruction Set Extensions Implemented as Reconfigurable Hardware
   Christophe Wolinski *, Krzysztof Kuchcinski **
   *IRISA, IFSIC, France
   **Lund University, Sweden
7. Reducing Critical Path Delay in FPGAs with SRAM Tables Shared by NPN-Equivalent Functions
   Jason J. Meyer and Fatih Kocan
   Southern Methodist University, USA
8. Pure ASIC-based Retargetable Computing: Architectures, Advantages, and Challenges
   Yong-Kyu Jung
   Texas A&M University, USA