A Unified Retargetable Design Methodology for Dedicated and Re-Programmable Multiprocessor Arrays - Case Study and Quantitative Evaluation
Prof. Jürgen Teich, Univ. of Erlangen-Nürnberg, Germany
Tuesday: 10:40 - 11:25am
Room: Gold Room
Abstract
The efficient mapping of algorithms onto parallel architectures is of utmost importance since many state-of-the-art embedded digital systems have to deploy parallelism in order to increase their computational power. This talk deals with the mapping of nested loop programs onto massively parallel processor arrays. We present a unified design methodology in order to achieve highly parallel implementations for two kinds of architectures: (a) dedicated, application-specific arrays and (b) coarse-grained, "weakly programmable" processor arrays. We describe which steps of the design flow can be conducted for both architecture types in common. The hardware synthesis of dedicated hardware accelerators is mostly automated and only relatively few architectural constraints have to be considered. Whereas, when targeting coarse-grained processor arrays, a large number of architectural parameters have to be incorporated during the backend code generation.
The proposed unified retargetable design methodology is applied in several case studies. Implementations for both target architectures with respect to performance, area cost, and reconfiguration time are evaluated. The results show that both approaches have their specific benefits and drawbacks.
Bio
Jürgen Teich received his masters degree (Dipl.-Ing.) in 1989 from the University of Kaiserslautern (with honours). From 1989 to 1993, he was PhD student at the University of Saarland, Saarbruecken, Germany from where he received his PhD degree (summa cum laude). In 1994, Dr. Teich joined the DSP design group of Prof. E. A. Lee and D.G. Messerschmitt in the Department of Electrical Engineering and Computer Sciences (EECS) at UC Berkeley where he was working in the Ptolemy project (PostDoc). From 1995 to 1998, he held a position at Institute of Computer Engineering and Communications Networks Laboratory (TIK) at ETH Zurich, Switzerland, finishing his Habilitation entitled `Synthesis and Optimization of Digital Hardware/ Software Systems' in 1996. From 1998 to 2002, he was full professor in the Electrical Engineering and Information Technology department of the University of Paderborn, holding a chair in Computer Engineering. Since 2003, he is appointed full professor in the Computer Science Institute of the Friedrich-Alexander University Erlangen-Nuremberg holding a chair in Hardware-Software-Co-Design. Dr. Teich has been a member of multiple program committees of well-known conferences and workshops including CODES+ISSS 2007. In 2004, Prof. Teich has been elected reviewer for the German Science Foundation (DFG) for the area of Computer Architecture and Embedded Systems. Prof. Teich is involved in many interdisciplinary national basic research projects as well as industrial projects. He is supervising more than 20 PhD students currently.
