Novel Uses of Memory for Adaptive Power-down in FPGAs
Prof. John Villasenor, Univ. of California Los Angeles, USA
Monday: 01:15 - 02:00pm
Room: Gold Room
Abstract
A new configurable design approach that incorporates both non-volatile and volatile memory for use with core computational and routing logic is presented. The use of non-volatile memory offers the potential to dramatically improve area and cost while delivering the performance benefits of traditional SRAM based FPGAs. Moreover, the resulting hybrid FPGA architectures can support adaptive power-down algorithms which can be used to improve overall power efficiency.
Bio
John Villasenor received the B.S. degree in 1985 from the University of Virginia, the M.S. in 1986 from Stanford University, and the Ph.D. in 1989 from Stanford, all in Electrical Engineering. From 1990 to 1992, he was with the Jet Propulsion Laboratory in Pasadena, California. He joined the Electrical Engineering Department at UCLA in 1992, and is currently Professor. His research interests lie in communications, computing, imaging, coding, and networking.
