ERSA’2008
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

Back to Invited Talks ... Back to Schedule ...

Cellular Automata Architectures

Greg Leeming, Microelectronics Advanced Research Corporation, USA
Ralph Cavin, Semiconductor Research Corporation, USA
Kosmas Galatsis, UCLA, USA

Abstract:

How will multicore processing evolve and what will be the dominant computer architecture of the future? As technology reaches the limits of CMOS and beyond, the physical realities of computing hardware might dictate the answer to these questions. The integration level for nanoscale electronic devices could eventually be in the range of 10¹⁰ to 10¹¹ devices per square centimeter¹. At this level long interconnects represent a significant challenge to operation (energy consumption), design, and manufacturing (irregular arrays of interconnects with arbitrary connections). Also, nanoscale elements are likely to suffer from significantly higher failure rates than their contemporary counterparts. In addition, low-energy operation requirements and small transistor dimensions are likely to result in higher thermal and quantum error rates. Moreover, the problem of designing complex irregular structures at these density levels is becoming increasingly untenable. Given these realities, future nanoscale technology may drive a migration to different information processing and computing approaches. One such possibility is the class of digital cellular automata.

The suitability of digital cellular automata as future mainstream computing architectures was recently examined by Cavin, Zhirnov, Leeming and Galatsis¹. This paper extends the analysis presented in ¹ by examining current technology trends, market momentum and the implementational challenges associated with digital cellular automata, to predict the influence digital cellular automata architectures are likely to have over the next 15 years.

References

1. R. Cavin, V. Zhirnov, G. Leeming and K. Galatsis, An Assessment of Integrated Digital Cellular Automata Architectures, IEEE Computer, Volume 41, January, 2008, pp. 38-44.

BIO:

Greg Leeming is employed by the Intel Corporation where he is the Strategic Program Manager for the Corporate Research Council which oversees Intel’s investment in long range University Research. Greg has 20 years of industry experience working in research and new technology development organizations. Greg has a BS math from Bates College, Lewiston ME, BSEE from Northeastern University, Boston MA and an MSEE from Brown University, Providence RI.

A native of Natchez Mississippi, Ralph K. Cavin received his BSEE (1961) and MSEE (1962) from Mississippi State University and his Ph.D. in Electrical Engineering from Auburn University in 1968. He served as a Senior Engineer at the Martin-Marietta Company in Orlando, Florida, from 1962-1965. At Martin, Cavin was involved in the design and manufacture of missile guidance and control systems. After taking his Ph.D., Cavin joined the faculty of the Department of Electrical Engineering at Texas A & M University where he obtained the rank of Full Professor and also served the department as Assistant Head for Research. In 1983, he joined the Semiconductor Research Corporation (SRC) where he served as Director of Design Sciences research programs until 1989. He became Head of the Department of Electrical and Computer Engineering at North Carolina State University from 1989-1994 and was Dean of Engineering at North Carolina State University from 1994-1995. From 1996 to 2006, he served as SRC's Vice President of Research Operations and in January 2007 became their Chief Scientist.

Cavin’s technical interests include CMOS and emerging information processing devices, technologies and architectures, design methodologies and tools, signal processing applications, control systems, and modeling and simulation of physical systems. He has authored or co-authored over 100 refereed technical papers and contributions to books. Cavin is a Fellow of the Institute for Electrical and Electronics Engineers (IEEE) and has participated actively in society programs. He serves as a consultant to a number of government, industrial, and academic institutions and is a member of the Board of Directors of the International Engineering Consortium and the IEEE Computer Advisory Board.

Kosmas Galatsis received his B.Eng in Computer Systems (First Class Honors) and his PhD in Electrical Engineering from the Royal Melbourne Institute of Technology University (RMIT), Australia. His thesis focused on nanocrystalline binary metal oxide semiconductors for gas sensing applications. During his graduate studies, Kosmas was awarded the "Best Postgraduate Technical Paper in Australia" by the IEEE Australia. He completed his postdoc at RMIT then contracted for Teledyne Technologies in the USA as a principal development engineer working on NDIR sensors. He then went on to receive his MBA from LaTrobe University, Australia. Kosmas is the Chief Operating Officer for two industry lead nanoelectronics Centers headquartered at University of California, Los Angeles (UCLA). The FENA Center (www.fena.org) explores beyond CMOS materials, devices and architectures and WIN (www.win-nano.org) seeks to develop spintronic devices. In addition, his research interests include emerging logic and memory devices, nanoarchitectrures, nanopatterning, ferromagnetic materials such as chromium dioxide (CrO2), diluted magnetic semiconductors such as MnGe and synthesis and CNT applications.

Back to Invited Talks ... Back to Schedule ...