ERSA’2008
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

On FPGA Design With Self-Checking And Fault Tolerance Capability

Prof. Parag K. Lala, Texas A&M Univ.-Texarkana, USA

This paper discusses the work done by the author in the area of self-checking and faulttolerant FPGA design. It also proposes an FPGA architecture that is composed of functional cells with built in error correction capability. A functional cell in the proposed architecture can be used to implement logic functions as well as to route signals to other functional cells. It is composed of three units: a logic block, a fault-tolerant address generator and a director unit. The logic block uses a look-up table to implement logic functions. The fault-tolerant address generator corrects any single bit error in the incoming data to the functional cell; it uses a similarity checker circuit to correct single errors rather than the traditional triple-modular redundancy technique. The director block can transmit output data from the logic block to another functional cell located at its South, North, East or West, or to cells in all four directions. The proposed architecture is well suited for tolerating transient errors within a functional cell, a feature that is not available in any currently available commercial FPGA devices.

Parag K. Lala is the Cary and Lois Patterson Chair of Electrical Engineering at Texas A&M University at Texarkana. Previous to his current position he was the Thomas Mullins Chair Professor of Computer Engineering, University of Arkansas at Fayetteville. He received an M.Sc.(Eng.) degree from the King’s College, University of London and a Ph.D. from The City University of London. His current research interests are in On-line testable logic, Biologically-inspired digital system design, Fault-tolerant Computing, Hardware-based molecular sequence matching and Cryptology. He has authored or coauthored over 130 papers.

He is the author of six books: Fault-Tolerant & Fault-Testable Hardware Design (Prentice- Hall,1985), Digital System Design using PLDs (Prentice-Hall,1990), Practical Digital Logic Design and Testing (Prentice-Hall, 1996), Digital Circuit Testing and Testability (Academic Press, 1997), and Self-Checking, Fault-Tolerant Digital Design (Morgan-Kaufmann, 2001), and Principles of Modern Digital Design (John Wiley and Sons,2007) He was selected Outstanding Educator in 1994 by the Central North Carolina section of the IEEE. In 1998 he was awarded a D.Sc.(Eng.) degree in Electrical Engineering by the University of London for contributions to digital hardware design and testing He was named a Fellow of the IEEE in 2001 for contributions to the development of self-checking logic and associated checker design. He is also a Fellow of the IET, the largest professional engineering society in Europe.