ERSA News

ERSA’08 Final Programme

ERSA’08 Accepted Papers

ERSA’08 Posters

  1. Non-volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals
    Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama
    Tohoku University, Japan

  2. An Embedded Dynamically Self-Reconfigurable Parallel Master-Slaves SoC Architecture
    Kimon Karras, Elias Manolakos
    National and Kapodistrian University of Athens, Greece

  3. Performance Improvement under Hardware Constraints of Application-Specific Instructions
    Chijie Lin, Jiying Wu, Jerung Shiu, Desheng Chen and Yiwen Wang
    Feng Chia University, Taichung, Taiwan

  4. Analysis of a Reconfigurable Platform for Frequent Pattern Mining
    Song Sun and Joseph Zambreno
    Iowa State University, USA

  5. Design of a Cellular Automata ASIC for Conformal Computing
    Mariam Hoseini, Chao You, Mark Pavicic
    North Dakota State University, USA

  6. FPGA Schemes with Optimized Routing for the Advanced Encryption Standard
    Jason Van Dyken, José G. Delgado-Frias, Sirisha Medidi
    Washington State University, USA

  7. Synthesis of Relocatable Tasks and Implementation of a Task Communication Bus in a General Purpose Hardware System
    Angel Luis González Bravo, Hortensia Mecha López, Julio Septién del castillo, Sara Román Navarro, Daniel Mozos Muñoz
    Universidad Complutense de Madrid, Spain

  8. Performance Evaluation of FPGA-based Hardware Accelerator: A Case Study
    Yidong Liu, Srinivasan Santhanam, Jooheung Lee
    University of Central Florida, USA

  9. FPGA Resource Management Using Internal RAM as Data Cache
    L. Sanchez, J. Septi?n, D. Mozos, and H. Mecha
    University Complutense of Madrid, Spain

  10. Resource Management for Hw Multitasking in Three Dimensional FPGAs
    J. A. Valero, J. Septien, D. Mozos, H. Mecha
    University Complutense of Madrid, Spain

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