ERSA News

ERSA’08 Final Programme

ERSA’08 Accepted Papers

ERSA’08 Regular Papers

  1. Communication and Synchronization in Multithreaded Reconfigurable Computing Systems
    Enno Luebbers and Marco Platzner
    University of Paderborn, Germany

  2. A New High Performance Multi Gigabit String Matching Engine
    Adouko G., Charot F., Wolinski C.
    IRISA, INRIA, University of Rennes 1, France

  3. Towards Understanding and Managing the Dynamic Behavior of Run-Time Reconfigurable Architectures
    Kehuai Wu, Esben Rosenlund Hansen, Jan Madsen.
    Technical Univ. of Denmark, Denmark

  4. System on a Programmable Chip Adaptation Through Active Partial Reconfiguration
    Erik Anderson, Matthew French, Dong-In Kang
    University of Southern California, USA

  5. A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability
    Wai-Chung Tang, Catherine Lin Zhou, Yu-Liang Wu
    The Chinese University of Hong Kong, Hong Kong

  6. A New Efficient Architecture for Univariate Polynomial Interpolation Over GF(2^m)
    Edgar Ferrer, Dorothy Bollman
    University of Puerto Rico at Mayaguez, USA

  7. FPGA Design Framework for Partial Run-Time Reconfiguration
    Chris Conger, Ann Gordon-Ross, Alan George
    University of Florida, USA

  8. Elemental Computing
    Joseph Hassoun, Steven Kelem, Brian Box, Stephen Wasson, Robert Plunkett, Chris Phillips
    Element CXI, USA

  9. Multiparadigm Computing for Space-Based Synthetic Aperture Radar
    Adam Jacobs, Grzegorz Cieslewski, Casey Reardon, and Alan D. George
    University of Florida, USA

  10. An Introduction to Radiation-Induced Failure Modes and Mitigation Methods For Xilinx SRAM-Based FPGAs
    Heather Quinn(2), Keith Morgan(2), Paul Graham(2), Jim Krone(2), Michael Caffrey(2), and Michael Wirthlin(1)
    (1)Brigham Young University, USA
    (2)Los Alamos National Laboratory, USA

  11. Highly Parallel FPGA Based IEEE-754 Compliant Double-Precision Floating-Point Division
    Sandeep Venishetti and Ali Akoglu
    University of Arizona, USA

  12. A Formal Semantics for Control and Data flow in the Gannet Service-based System-on-Chip Architecture
    Wim Vanderbauwhede
    University of Glasgow, UK

  13. Optimizing Pipelining in HDL Generated Automatically from C Source Codes
    Wesley Holland and Yoginder S. Dandass
    Mississippi State University, USA

  14. SystemC-based Custom Reconfigurable IP Cores for Wireless Applications
    Ali Ahmadinia, Balal Ahmad, Ahmet Erdogan, Tughrul Arslan
    The University of Edinburgh, Scotland, UK

  15. High Level Languages for Reconfigurable Computing: An Equivalent to Third Generation Software Languages?
    Gavin Smith and Grant Wigley
    University of South Australia, Australia

  16. A Framework to Improve IP Portability on Reconfigurable Computers
    Miaoqing Huang, Ivan Gonzalez, Sergio Lopez-Buedo, Tarek El-Ghazawi
    The George Washington University, USA

  17. Evaluation of MuCCRA-D: A Dynamically Reconfigurable Processor With Directly Interconnected PEs
    Masaru Kato, Yohei Hasegawa, Hideharu Amano
    Keio University, Japan

  18. A Method for Capturing State Data on Dynamically Recongurable Processors
    Vu Manh Tuan and Hideharu Amano
    Keio University, Japan

  19. Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning
    Waidyasooriya Hasitha Muthumala, Masanori Hariyama, Michitaka Kameyama
    Tohoku University, Japan

  20. MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration --- Proposal and a 6502 Perspective ---
    Fuminori Kobayashi*, Yasuyuki Morikawa* and Minoru Watanabe**
    *Kyushu Institute of Technology--Iizuka, Japan
    **Shizuoka University, Japan

  21. A Hardware Accelerator for k-th Nearest Neighbor Thinning
    Tobias Schumacher, Robert Meiche, Paul Kaufmann, Enno Luebbers, Christian Plessl and Marco Platzner
    University of Paderborn, Germany

  22. Fast Realtime LIDAR Processing on FPGAs
    Kuei-Tsung Shih, Arjun Balachandran, Karthik Nagarajan, Brian Holland, Clint Slatton, Alan George
    University of Florida, USA

  23. Gradient Run-length Data Compression for Real-time Airborne Image Processing
    Zachary K. Baker and Justin L. Tripp
    Los Alamos National Laboratory, USA

  24. A Parallel Array to Accelerate GFA Modeling in Video Coding
    Abdel Ejnioui and Paul Bao
    University of South Florida Lakeland, USA

  25. Qnet: A Modular Architecture for Reconfigurable Computing
    Scott Lloyd, Quinn Snell
    Brigham Young University, USA

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