ERSA’2008
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

Next Generation Research Challenges in Reconfigurable Computing

Chairman: Prof. David Andrews, University of Kansas, USA

Gerald Estrin started the field of reconfigurable computing in 1961 when he created the fixed plus variable computer. After Estrins pioneering work, the field of reconfigurable computing largely lay dormant until the introduction of the modern FPGA in the early 1990’s. The discipline of reconfigurable computing experienced a resurgence during that time, but the limited sizes of the FPGAs relegated their use as application specific accelerators. Supporting research during this period largely focused on new synthesis techniques for enabling programmers to express and map application kernels as custom co-processors for the FPGA from within familiar high level languages.

We are now entering a new generation in which FPGA’s can support a complete multiprocessor system on chip architecture and are not limited to simply hosting application accelerators. This capability is coinciding with a confluence of demands for next generation distributed embedded systems of highly networked multiprocessor systems on chips with autonomous dynamic adaptability and operational security guarantees. The historical approaches developed during the 1990’s that were focused on language level synthesis are simply not a substitute for the system modeling abstractions, architecture synthesis, run time systems and software concurrency representations required for turning platform FPGA’s into complete multiprocessor systems on chips. This session contains invited presentations by recognized experts in the field who will present their visions on the fundamental research challenges the discipline of reconfigurable computing must address to enable platform FPGAs to achieve their full potential as enabling frameworks for next generation distributed real time embedded systems