ERSA’2008
The International Conference on
Engineering of Reconfigurable Systems and Algorithms

Image/Video Coding Acceleration with Reprogrammable Logic Devices

Chairman: Dr. Jooheung Lee, University of Central Florida, USA

Many applications implemented in ASICs are increasingly choosing FPGA solutions due to factors such as reduced cost, improved ease of design changes, and faster time-to-market. Especially, high capacity of FPGAs with general-purpose microprocessor cores implemented on-chip can be very suitable for the uses with high computational complexities, such as image and video coding applications. In addition, reconfigurability of FPGAs can provide new possibilities of innovations at the algorithm or hardware levels. However, FPGA-based algorithm optimizations and architectural designs which provide scalable performance in varying environment settings or suitable trade-offs among performance, power, and limited hardware resources remain challenging topics. This session focuses on image and video signal processing algorithms, their design and implementations utilizing reconfigurable FPGA devices addressing these concerns.