ERSA: IEEE TVLSI SS1

IEEE TVLSI Special Section on
Configurable Computing Design

Guest Editorial Special Section on Configurable Computing Design I: High-Level Reconfiguration
Plaks, T. P.
Page(s): 1-2
Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware
Rauwerda, G. K.; Heysters, P. M.; Smit, G. J. M.
Page(s): 3-13
Abstract
A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance
Myjak, M. J.; Delgado-Frias, J. G.
Page(s): 14-23
Abstract
Run-Time Management of a MPSoC Containing FPGA Fabric Tiles
Nollet, V.; Avasare, P.; Eeckhaut, H.; Verkest, D.; Corporaal, H.
Page(s): 24-33
Abstract
Achieving Programming Model Abstractions for Reconfigurable Computing
Andrews, D.; Sass, R.; Anderson, E.; Agron, J.; Peck, W.; Stevens, J.; Baijot, F.; Komp, E.
Page(s): 34-44
Abstract
A Cooperative Management Scheme for Power Efficient Implementations of Real-Time Operating Systems on Soft Processors
Ou, J.; Prasanna, V. K.
Page(s): 45-56
Abstract
Reconfigurable Architecture for Network Flow Analysis
Yusuf, S.; Luk, W.; Sloman, M.; Dulay, N.; Lupu, E. C.; Brown, G.
Page(s): 57-65
Abstract
A Case Study of Hardware/Software Partitioning of Traffic Simulation on the Cray XD1
Tripp, J.; Gokhale, M. B.; Hansson, A. A.
Page(s): 66-74
Abstract
The Reconfigurable Instruction Cell Array
Khawam, S.; Nousias, I.; Milward, M.; Yi, Y.; Muir, M.; Arslan, T.
Page(s): 75-85
Abstract